In a semiconductor memory device having a memory chip such as a NAND-type flash memory built therein, there has been applied a structure in which a chip stacked body having thickness-reduced memory chips stacked in multiple tiers is disposed on an interposer substrate, in order to achieve miniaturization and high capacitance. Further, in order to transmit and receive electrical signals between the memory chips at a high speed, it has been performed to electrically connect the memory chips stacked in multiple tiers by providing through electrodes in each of the plural memory chips and connecting the through electrodes by bump electrodes.
In the semiconductor memory device, an interface (IF) circuit performing data communications between the memory chips and an external device is needed. The IF circuit is incorporated in a lowermost memory chip in the chip stacked body, for example. An increase in size of the lowermost memory chip is unavoidable as compared with the other memory chips, and thus the size of the device is increased. Further, two types of the memory chips are needed, so that there are caused problems of deterioration of development efficiency, an increase in manufacturing cost, and so on. It has also been considered that a semiconductor chip having the IF circuit (IF chip) is disposed on the chip stacked body. In such a case, it has been required to achieve a reduction in manufacturing cost and improvement of the speed of data communications with an external device by improving a disposition of the IF chip, connection structures between the IF chip and the memory chips or the interposer substrate, and the like.